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PE42551
Product Specification
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE42551 SPDT switch. The RF common port is
connected through a 50 ? transmission line to J2.
Port 1 and Port 2 are connected through 50 ?
transmission lines to J1 and J3. A through
transmission line connects SMA connectors J4
and J5. This transmission line can be used to
estimate the loss of the PCB over the
environmental conditions being evaluated.
The board is constructed of a two metal layer
FR4 material with a total thickness of 0.032”. The
transmission lines were designed using a
coplanar waveguide with ground plane (28 mil
core, 47.6 mil width, 30 mil gap).
Good RF layout and prudent use of vias is critical
for obtaining the specified isolation performance
for the device shown in this datasheet.
J6 provides a means for controlling DC and
digital inputs to the device. The provided jumpers
short the package pin to ground for logic low.
When the jumper is removed, the pin is pulled up
to V DD for logic high. When the jumper is in place,
3 μA of current will flow through the 1M ? pull up
resistor. This extra current should not be
Figure 5. Evaluation Board Layouts
Peregrine Specification 101-0151
Figure 6. Evaluation Board Schematic
Peregrine Specification 102-0198
J6
HEADER 7X2
attributed to the requirements of the device.
C1
DNI
R1
1M
R2
1M
1
3
5
7
9
11
13
1
3
5
7
9
11
13
2
4
6
8
10
12
14
2
4
6
8
10
12
14
C2
DNI
C3
DNI
1
GND
GND
15
J1
SMASM
1
50 OHM T-Line
2
3
GND
RF1
U1
PE42551
GND
RF2
14
13
50 OHM T-Line
1
J3
SMASM
J2
50 OHM T-Line
4
5
GND
GND
GND
GND
12
11
SMASM
1
J4
SMASM
1
50 OHM T-Line
1
J5
SMASM
Document No. 70-0350-02 │ www.psemi.com
?2010-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 9
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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